1. Field of the Invention
The present invention relates to a probing plate for wafer testing and, more particularly, to a probing plate for wafer testing having a plurality of probes arranged so as to correspond to a plurality of electrodes of a semiconductor device (semiconductor chip) fabricated on a semiconductor wafer.
2. Description of the Background Art
Generally, a checking equipment (hereinafter, referred to as "wafer prober") for measuring the electrical characteristics of a semiconductor device formed on a semiconductor wafer in a semiconductor integrated circuit (IC) manufacturing process employs a probing plate. The probing plate is formed by fixedly arranging probes in a pattern corresponding to that of the electrodes, i.e., the bonding pads or solder bumps, of the semiconductor device on an insulating holding plate.
A conventional wafer tester will be described with reference to FIG. 9A showing a conventional probing plate for wafer testing incorporated into a wafer prober and FIG. 9B showing probes in contact with bonding pads formed on a wafer.
A wafer 1 mounted with a plurality of semiconductor device, such as LSIs (large-scale integrated circuits) is fixed on a wafer chuck 8. The wafer chuck 8 can be moved vertically and horizontally by a moving mechanism 9. A large number on the order of several hundreds of bonding pads 2 are formed on the upper surface of the wafer 1 for each semiconductor chip. Slender probes 3 are arranged and held on a probe holding plate 4 so as to correspond to the bonding pads 2, respectively. The probe holding plate 4 is positioned above the wafer 1. The probes 3 are formed of tungsten, chromium or a tungsten-chromium alloy. The probe holding plate 4 is formed of an insulating material, such as glass or an epoxy resin. A conductive pattern 5 is formed of a metal, such as copper over one surface of the probe holding plate 4, and the probes 3 are connected electrically to the conductive pattern 5 by soldering or the like. The size of the contact area of the electrode pads 2 with which the tip of the probe 3 is brought into contact is in the range of about 50 to about 100 .mu.m in diameter. The external diameter of the base of the probe 3 connected to the probe holding plate 4 is in the range of about 150 to about 200 .mu.m. A conductive pattern 5, which is the same as the conductive pattern 5 connected to the proves 3, is formed on the other surface of the probe holding plate 4 and is connected through through holes to the former conductive pattern 5. The conductive pattern 5 is in electrical contact with contact pins (hereinafter, referred to as "pogo pins") 7 provided on the test head 6 of a LSI tester, not shown. The probe holding plate 4 is held fixedly on the plate holding member 12.
The testing procedure using the probing plate for wafer testing for testing the electrical characteristics of a semiconductor devices on a wafer will be described hereinafter. The position of the wafer chuck 8 is adjusted by the moving mechanism 9 so that the bonding pads 2 of one or a plurality of semiconductor devices formed on the wafer 1 are brought into contact respectively with the corresponding probes 3 fixed on the probe holding plate 4. The wafer chuck 8 is moved vertically so that the undersurfaces of the bonding pads 2 are in appropriate contact with the corresponding probes 3, respectively. Consequently, the semiconductor devices formed on the wafer 1 are connected electrically through the conductive patterns 5 and the pogo pins 7 of the test head 6 to the LSI tester for signal transmission between the semiconductor devices on the wafer 1 and the LSI tester for testing the electrical characteristics of the semiconductor devices assembled on the wafer 1.
However, since the conventional probing plate for wafer testing employs probes, the diameter of the probes must be reduced according to the reduction in the size and pitch of the bonding pads formed on the wafer, which entails increase in the contact resistance between the bonding pads and the probes. Further more, difficulty in manufacturing the probes and in mounting the probes on the probe holding plate is enhanced as the diameter of the probes is reduced. That is, reduction in the size of probes makes it difficult to accurately attach a plurality of minute probes to the probe holding plate so that the probes can be highly accurately positioned relative to a plurality of bonding pads formed on the wafer by precision processes.
A wafer probing unit developed to solve such problems is disclosed in Japanese Patent Laying-Open Gazette No. 162045/1983. This wafer probing unit is shown in FIGS. 10A and 10B. As shown in FIGS. 10A and 10B, in this wafer probing unit, probe fingers 21 are formed in a flat quartz plate 20 by selectively removing portions of the flat quartz plate 20 by photolithographic techniques, and leads 22 for transmitting electric signals from the bonding pads of semiconductor devices to an external equipment are formed on the surfaces of the probe fingers 21 by photolithographic techniques. Metallic needles 23 are fitted in through holes 24 formed near the free ends of the probe fingers 21 and are fixed to the probe fingers 21 and connected electrically to the leads 22 by a conductive adhesive, respectively.
Since the probe fingers are formed simultaneously by photolithographic techniques, the probe fingers 21 are formed in a high positional accuracy. However, processing the free ends of the probe fingers 21 to attach the metallic needles 23 to the probe finger 21 is very difficult.
FIG. 11 shows another conventional wafer probing plate which is disclosed in Japanese Patent Laying-Open Gazette No. 144142/1984. In this wafer probing plate, conductive wiring patterns 32 are formed on both sides of a ceramic plate 30 and are interconnected through through holes. Copper or gold contact pads 33 serving as probes are formed on the conductive wiring pattern 32 for electrical contact with the bonding pads of semiconductor devices. Connecting pins 31 are fixed to one side edge of the ceramic plate 30 and are connected to the conductive wiring pattern 32. The contact pads 33, as well as the conductive wiring patterns 32, can be formed accurately at positions respectively corresponding to those of the bonding pads of the semiconductor devices by a vapor deposition process or a printing process. However, it is difficult to form the copper or gold contact pads 33 on the ceramic plate 30 in a high density so that the contact pads 33 coincide respectively with bonding pads arranged at very small intervals on the order of 30 .mu.m. Although the height of the contact pads 33 from the surface of the ceramic plate 30 is the thickness of the conductive films forming the contact pads 33, it is difficult to form the conductive films in an accurate thickness so that the contact pads 33 will not come into contact accidentally with the bonding pads of the semiconductor devices other than those to be tested.